CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links [electronic resource] / by Cecilia Gimeno Gasca, Santiago Celma Pueyo, Concepción Aldea Chagoyen
- Gimeno Gasca, Cecilia
- Cham : Springer International Publishing : Imprint: Springer, 2015.
- Physical Description:
- XXII, 148 pages 136 illustrations, 85 illustrations in color : online resource
- Additional Creators:
- Celma Pueyo, Santiago, Aldea Chagoyen, Concepción, and SpringerLink (Online service)
- Analog Circuits and Signal Processing, 1872-082X
- Introduction -- Theoretical Study of Continuous-Time Equalizers -- Continuous-Time Linear Equalizers -- Adaptation Loop -- Receiver Front-End For 1.25 GB/s SI-POF -- Conclusions. .
- This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF). · Covers complete design flow of continuous-time adaptive equalizers, from analysis of theoretical fundamentals to the final architecture; · Includes analysis, design, and implementation of the main adaptive equalizer blocks, revealing key challenges and solutions in the design of such high performance cells; · Discusses the most important points in the design of an adaptive equalizer, considering restrictions of the optical link and the limitations in submicron CMOS implementations.
- Digital File Characteristics:
- text file PDF
- AVAILABLE ONLINE TO AUTHORIZED PSU USERS.
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