Actions for Pillar Structured Thermal Neutron Detector [electronic resource].

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Pillar Structured Thermal Neutron Detector [electronic resource].

Published
Washington, D.C. : United States. Dept. of Energy, 2008.
Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
Physical Description
PDF-file: 6 pages; size: 0.3 Mbytes
Additional Creators
Lawrence Berkeley National Laboratory, United States. Department of Energy, and United States. Department of Energy. Office of Scientific and Technical Information
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Summary
This work describes an innovative solid state device structure that leverages advanced semiconductor fabrication technology to produce an efficient device for thermal neutron detection which we have coined the 'Pillar Detector'. State-of-the-art thermal neutron detectors have shortcomings in simultaneously achieving high efficiency, low operating voltage while maintaining adequate fieldability performance. By using a three dimensional silicon PIN diode pillar array filled with isotopic ¹°boron (¹°B), a high efficiency device is theoretically possible. Here we review the design considerations for going from a 2-D to 3-D device and discuss the materials trade-offs. The relationship between the geometrical features and efficiency within our 3-D device is investigated by Monte Carlo radiation transport method coupled with finite element drift-diffusion carrier transport simulations. To benchmark our simulations and validate the predicted efficiency scaling, experimental results of a prototype device are illustrated. The fabricated pillar structures reported in this work are composed of 2 {micro}m diameter silicon pillars with a 2 {micro}m spacing and pillar height of 12 {micro}m. The pillar detector with a 12 {micro}m height achieved a thermal neutron detection efficiency of 7.3% at a reverse bias of -2 V.
Report Numbers
E 1.99:llnl-proc-404677
llnl-proc-404677
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Note
Published through SciTech Connect.
06/10/2008.
"llnl-proc-404677"
Presented at: International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, Oct 20 - Oct 23, 2008.
Wang, T; Conway, A; Cheung, C; Graff, R; Deo, N; Reinhardt, C; Nikolic, R.
Funding Information
W-7405-ENG-48
View MARC record | catkey: 14105088