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IC chip stress during plastic package molding [electronic resource].

Published
Washington, D.C. : United States. Dept. of Energy, 1998.
Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
Physical Description
8 pages : digital, PDF file
Additional Creators
Sandia National Laboratories, United States. Department of Energy, and United States. Department of Energy. Office of Scientific and Technical Information
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Summary
Approximately 95% of the world`s integrated chips are packaged using a hot, high pressure transfer molding process. The stress created by the flow of silica powder loaded epoxy can displace the fine bonding wires and can even distort the metalization patterns under the protective chip passivation layer. In this study the authors developed a technique to measure the mechanical stress over the surface of an integrated circuit during the molding process. A CMOS test chip with 25 diffused resistor stress sensors was applied to a commercial lead frame. Both compression and shear stresses were measured at all 25 locations on the surface of the chip every 50 milliseconds during molding. These measurements have a fine time and stress resolution which should allow comparison with computer simulation of the molding process, thus allowing optimization of both the manufacturing process and mold geometry.
Report Numbers
E 1.99:sand--98-0383c
E 1.99: conf-980550--
conf-980550--
sand--98-0383c
Subject(s)
Other Subject(s)
Note
Published through SciTech Connect.
02/01/1998.
"sand--98-0383c"
" conf-980550--"
"DE98002897"
"DP0102022"
48. Electronic component and technology (ECTC) conference, Seattle, WA (United States), 25-28 May 1998.
Peterson, D.W.; Palmer, D.W.; Benson, D.A.; Sweet, J.N.
Funding Information
AC04-94AL85000
View MARC record | catkey: 14107454