Constant fan-in digital neural networks are VLSI-optimal [electronic resource].
- Washington, D.C. : United States. Dept. of Energy, 1995. and Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
- Physical Description:
- 12 pages : digital, PDF file
- Additional Creators:
- Los Alamos National Laboratory, United States. Department of Energy, and United States. Department of Energy. Office of Scientific and Technical Information
- Restrictions on Access:
- Free-to-read Unrestricted online access
- The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT² complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.
- Published through SciTech Connect., 12/31/1995., "la-ur--97-61", " conf-9507268--1", "DE97003400", Mathematics of neural networks and applications, Oxford (United Kingdom), 3-7 Jul 1995., and Beiu, V.
- Funding Information:
View MARC record | catkey: 14109664