Actions for High performance static latches with complete single event upset immunity [electronic resource].

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High performance static latches with complete single event upset immunity [electronic resource].

Published
Washington, D.C. : United States. Dept. of Energy, 1991.
Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
Physical Description
13 pages : digital, PDF file
Additional Creators
Sandia National Laboratories, United States. Department of Energy, and United States. Department of Energy. Office of Scientific and Technical Information
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Summary
This invention is comprised of a logical memory latch and cell, using logic and circuit modifications, provides SEU immunity without loss of speed. A single logic state is hardened against SEU using technology methods and the information concerning valid states is then based to simplify hardened circuit design.
Report Numbers
E 1.99:patents-us--a7793084
patents-us--a7793084
Subject(s)
Other Subject(s)
Note
Published through SciTech Connect.
12/31/1991.
"patents-us--a7793084"
"DE94003033"
": US patent application 7-793,084"
Weaver, H.T.; Corbett, W.T.
Funding Information
AC04-76DP00789
View MARC record | catkey: 14110254