Worst-Case Bias During Total Dose Irradiation of SOI Transistors [electronic resource].
- Washington, D.C. : United States. Dept. of Energy, 2000. and Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
- Physical Description:
- 4 pages : digital, PDF file
- Additional Creators:
- Sandia National Laboratories, United States. Department of Energy, and United States. Department of Energy. Office of Scientific and Technical Information
- Restrictions on Access:
- Free-to-read Unrestricted online access
- The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.
- Published through SciTech Connect., 08/15/2000., "sand2000-2074c", 2000 IEEE Nuclear and Space Radiation Effects Conference (NSREC), Reno, NV (US), 07/24/2000--07/28/2000., and SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; LERAY,J.-L; PAILLET,P.; MUSSEAU,O.; PELLOIE,J.L.; FERLET-CAVROIS,V.; COLLADANT,T.; DE PONCHARRA,J. JU PORT.
- Funding Information:
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