SLAC Scanner Processor applications in the data acquisition system for the upgraded Mark II detector [electronic resource].
- Menlo Park, Calif. : Stanford Linear Accelerator Center, 1985. and Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
- Physical Description:
- Pages: 4 : digital, PDF file
- Additional Creators:
- Stanford Linear Accelerator Center and United States. Department of Energy. Office of Scientific and Technical Information
- Restrictions on Access:
- Free-to-read Unrestricted online access
- The SLAC Scanner Processor is a general purpose, programmable FASTBUS crate/cable master/slave module. This device plays a central role in the readout, buffering and pre-processing of data from the upgraded Mark II detector's new central drift chamber. In addition to data readout, the SSPs assist in a variety of other services, such as detector calibration, FASTBUS system management, FASTBUS system initialization and verification, and FASTBUS module testing. 9 refs., 1 fig., 2 tabs.
- Published through SciTech Connect., 09/01/1985., "slac-pub-3781", " conf-851009-14", "DE86002939", IEEE nuclear science symposium, San Francisco, CA, USA, 23 Oct 1985., and Lankford, A.J.; Barklow, T.; Glanzman, T.; Riles, K.
- Funding Information:
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