Stress Voiding During Wafer Processing [electronic resource].
- Washington, D.C. : United States. Dept. of Energy, 1999.
Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
- Physical Description:
- 27 pages : digital, PDF file
- Additional Creators:
- Sandia National Laboratories
United States. Department of Energy
United States. Department of Energy. Office of Scientific and Technical Information
- Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.
- Published through SciTech Connect.
- Type of Report and Period Covered Note:
- Funding Information:
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