High resolution digital delay timer [electronic resource].

Published:: Los Alamos, N.M. : Los Alamos National Laboratory, 1988.
Oak Ridge, Tenn. : Distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy.
Additional Creators:: Los Alamos National Laboratory and United States. Department of Energy. Office of Scientific and Technical Information

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Summary:

Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay (20) provides a first output signal (24) at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits (26, 28) latch the high resolution data (24) to form a first synchronizing data set (60). A selected time interval has been preset to internal counters (142, 146, 154) and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses (32, 34) count down the counters to generate an internal pulse delayed by an interval which is functionally related to the preset time interval. A second LCD (184) corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD (74) to generate a second set of synchronizing data (76) which is complementary with the first set of synchronizing data (60) for presentation to logic circuits (64). The logic circuits (64) further delay the internal output signal (72) to obtain a proper phase relationship of an output signal (80) with the internal pulses (32, 34). The final delayed output signal (80) thereafter enables the output pulse generator (82) to produce the desired output pulse (84) at the preset time delay interval following input of the trigger pulse (10, 12).

Report Numbers:

E 1.99:us 4719375
us 4719375

Other Subject(s):

Resolution Digital Delay Timer Method Apparatus Provided Generating Output Pulse Following Trigger Pulse Time Delay Interval Preset Resolution Relative Resolution Available Supplied Clock Pulses Lumped Constant Delay 20 Provides Output Signal 24 Predetermined Interpolation Intervals Corresponding Desired Resolution Time Interval Latching Circuits 26 28 Latch Resolution Data 24 Form Synchronizing Data Set 60 Selected Time Interval Preset Internal Counters 142 146 154 Corrected Circuit Propagation Delay Times Magnitude Desired Resolution Internal Clock Pulses 32 34 Count Counters Generate Internal Pulse Delayed Interval Functionally Related Preset Time Interval Lcd 184 Corrects Internal Signal Resolution Time Delay Internal Pulse Applied Third Lcd 74 Generate Set Synchronizing Data 76 Complementary Set Synchronizing Data 60 Presentation Logic Circuits 64 Logic Circuits 64 Delay Internal Output Signal 72 Obtain Proper Phase Relationship Output Signal 80 Internal Pulses 32 34 Final Delayed Output Signal 80 Thereafter Enables Output Pulse Generator 82 Produce Desired Output Pulse 84 Preset Time Delay Interval Following Input Trigger Pulse 10 12 Trigger Pulse Trigger Pulse Clock Pulse Clock Pulse Selected Time Logic Circuits Logic Circuits Propagation Delay Functionally Related Time Delay Time Delay Time Delay Pulse Generator Output Pulse Output Pulse Output Pulse Output Signal Output Signal Output Signal Output Signal Data Set Time Interval Time Interval Time Interval Clock Pulses Clock Pulses Delay Time Delay Time Desired Output Logic Circuit Logic Circuit Resolution Time Resolution Time Phase Relationship Delay Times Resolution Available Resolution Digital Resolution Data Lumped Constant Digital Delay

Note:

Published through SciTech Connect.
01/01/1988.
"us 4719375"
Martin, Albert D.

Funding Information:

W-7405-ENG-36

View MARC record | catkey: 14758880