Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor
- Moore, J. Strother
- JAN 1, 1992.
- Physical Description:
- 1 electronic document
- Restrictions on Access:
- Unclassified, Unlimited, Publicly available. and Free-to-read Unrestricted online access
- Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.
- NASA Technical Reports Server (NTRS) Collection.
- Document ID: 19920015452., Accession ID: 92N24695., TR-69., NAS 1.26:189588., and NASA-CR-189588.
- No Copyright.
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