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Formal verification of a set of memory management units

Author
Cohen, Gerald C.
Published
Mar 1, 1992.
Physical Description
1 electronic document
Additional Creators
Schubert, E. Thomas and Levitt, K.
Online Version

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Unclassified, Unlimited, Publicly available.
Free-to-read Unrestricted online access
Summary
This document describes the verification of a set of memory management units (MMU). The verification effort demonstrates the use of hierarchical decomposition and abstract theories. The MMUs can be organized into a complexity hierarchy. Each new level in the hierarchy adds a few significant features or modifications to the lower level MMU. The units described include: (1) a page check translation look-aside module (TLM); (2) a page check TLM with supervisor line; (3) a base bounds MMU; (4) a virtual address translation MMU; and (5) a virtual address translation MMU with memory resident segment table.
Other Subject(s)
Collection
NASA Technical Reports Server (NTRS) Collection.
Note
Document ID: 19920012949.
Accession ID: 92N22192.
NASA-CR-189566.
NAS 1.26:189566.
Terms of Use and Reproduction
No Copyright.
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