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Test aspects of the JPL Viterbi decoder

Author
Breuer, M. A.
Published
Feb 15, 1989.
Physical Description
1 electronic document
Online Version

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Unclassified, Unlimited, Publicly available.
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Summary
The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.
Other Subject(s)
Collection
NASA Technical Reports Server (NTRS) Collection.
Note
Document ID: 19890010086.
Accession ID: 89N19457.
JPL, The Telecommunications and Data Acquisition Report; p 59-79.
Terms of Use and Reproduction
No Copyright.
View MARC record | catkey: 15691516