Parallel VLSI architecture emulation and the organization of APSA/MPP
- Odonnell, John T.
- Jul 1, 1987.
- Physical Description:
- 1 electronic document
- Restrictions on Access:
- Unclassified, Unlimited, Publicly available.
Free-to-read Unrestricted online access
- The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.
- Other Subject(s):
- NASA Technical Reports Server (NTRS) Collection.
- Document ID: 19870017108.
Accession ID: 87N26541.
NASA. Goddard Space Flight Center, Frontiers of Massively Parallel Scientific Computation; p 75-84.
- No Copyright.
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