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Development of a fault-tolerant microprocessor based computer system for space flight

Author
Montgomery, V. T.
Published
JAN 1, 1981.
Physical Description
1 electronic document
Online Version

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Restrictions on Access
Unclassified, Unlimited, Publicly available.
Free-to-read Unrestricted online access
Summary
A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.
Other Subject(s)
Collection
NASA Technical Reports Server (NTRS) Collection.
Note
Document ID: 19810025284.
Accession ID: 81N33827.
NASA-CR-161873.
Terms of Use and Reproduction
No Copyright.
View MARC record | catkey: 15717896