VLSI analog circuits : algorithms, architecture, modeling, and circuit implementation / Hongjiang Song

Author:: Song, Hongjiang
Published:: New York : McGraw-Hill Education, [2017]
Edition:: Second edition.
Physical Description:: xx, 439 pages : illustrations ; 25 cm

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Contents:

Machine generated contents note: 1.1.Organization of This Book -- References -- 2.1.Characterization of Linear Continuous-Tune Systems -- 2.1.1.Gain Response -- 2.1.2.Phase Response -- 2.1.3.Fourier Transform -- 2.1.4.Laplace Transform -- 2.2.Analysis of Continuous-Time Filters -- 2.2.1.S-Domain Representations of Functional Blocks -- 2.2.2.Characteristics of the S-Domain Transfer Function -- 2.2.3.Poles and Zeros -- 2.2.4.Time-Domain Response and Stability Criteria -- 2.2.5.Bode Plots -- 2.3.Block Diagram and Signal Flow Graph -- 2.3.1.Construction of Integrator-Based SFG -- 2.3.2.Construction of General SFG -- References -- 3.1.VLSI Operational Amplifier Circuit Structures -- 3.1.1.VLSI OPAMP Circuit Models -- 3.1.2.CMOS Two-Stage OPAMP Circuit -- 3.1.3.CMOS Folded Cascode OPAMP Circuit -- 3.1.4.CMOS Rail-to-Rail OPAMP Circuit -- 3.1.5.CMOS Fully Differential OPAMP Circuit -- 3.2.VLSI Resistor Structures -- 3.2.1.Poly Resistors -- 3.2.2.Diffusion Resistors -- 3.2.3.Well Resistors -- 3.2.4.Metal Resistors -- 3.2.5.Thin-Film Resistors -- 3.3.VLSI Capacitor Structures -- 3.3.1.Poly-Poly Capacitors -- 3.3.2.Metal-Insulator-Metal Capacitors -- 3.3.3.MOS Gate Capacitors -- 3.3.4.Junction Capacitors -- 3.3.5.Metal-Metal Capacitors -- References -- 4.1.Basic MOS Voltage-Controlled Resistors -- 4.1.1.Single-Transistor Linear MOS VCR Circuit -- 4.1.2.Two-Transistor Linear MOS VCR Circuit -- 4.2.Differential Linear MOS VCR Structures -- 4.2.1.Two-Transistor Differential MOS VCR -- 4.2.2.Four-Transistor Differential MOS VCR -- 4.3.Grounded Linear MOS VCR Structures -- 4.3.1.Saturation MOS[—]Based Linear VCR -- 4.3.2.Symmetrical MOS[—]Based Linear VCR -- 4.4.Distributed MOS-RC Circuits -- 4.5.Basic MOS-C Signal Processing Circuit Structures -- 4.5.1.MOS-C Scaling Circuit -- 4.5.2.MOS-C Adder Circuit -- 4.5.3.MOS-C Integrator Circuit -- References -- 5.1.Basic VLSI Gm Circuit Structures -- 5.1.1.Basic MOS Gm Circuit Structure -- 5.1.2.Cascode MOS Gm Circuit Structures -- 5.1.3.VLSI Fully Differential Gm Circuit Structures -- 5.2.Linear-Based MOS Gm Circuit Structures -- 5.2.1.Source-Grounded MOS Gm Circuit -- 5.2.2.Fixed-Bias Source Degeneration Gm Circuit -- 5.2.3.Varying-Bias Source Degeneration Gm Circuit -- 5.3.Saturation-Based MOS Gm Circuit Structures -- 5.3.1.Fixed Common-Mode Gm Circuit -- 5.3.2.Floating Source Gm Circuit -- 5.3.3.Super-CMOS[—]Based Gm Circuit -- 5.3.4.Bias-Offset Cross Pairs[—]Based Gm Circuit -- 5.3.5.CMOS Inverter[—]Based Gm Circuit -- References -- 6.1.Basic MOS CTI Circuit Structures -- 6.1.1.Basic CTI Scaling Circuit -- 6.1.2.Basic CTI Integrator Circuit -- 6.1.3.Basic CTI Lossless Integrator Circuit -- 6.1.4.Fully Differential CTI Integrator Circuit -- 6.2.Introduction to Current Conveyor Circuits -- 6.2.1.Second-Generation Conveyor -- 6.2.2.CCII-Based Signal Processing Circuit Structures -- 6.3.CMOS CCII Circuit Structures -- 6.3.1.CMOS Single-End CCII Circuits -- 6.3.2.CMOS Fully Differential CCII Circuits -- 6.3.3.Feedback-Based VLSI CCII Circuits -- References -- 7.1.Discrete-Time Signals and Sampling Process -- 7.1.1.Discrete-Time Signals -- 7.1.2.VLSI Discrete-Time Signals -- 7.1.3.Sampling of Continuous-Time Signals -- 7.2.Discrete-Time System Responses -- 7.2.1.Z-Transform -- 7.2.2.Solution to DT Circuit Based on Z-Transform -- 7.2.3.Expression of VLSI Sampling Operation -- 7.3.Z-Domain Transfer Function and System Responses -- 7.3.1.Z-Domain Transfer Function -- 7.3.2.Gain and Phase Responses of the DT Systems -- 7.3.3.Time-Domain Response and Stability -- 7.4.Z-Domain Block Diagram and Signal Flow Graph -- 7.4.1.Construction of Z-Domain SFG -- 7.5.S-to-Z Transformations -- 7.5.1.Standard S-to-Z Transform -- 7.5.2.Matched-Z Transform -- 7.5.3.Forward Euler Integration -- 7.5.4.Backward Euler Integration -- 7.5.5.Bilinear Transformation -- 7.5.6.LDI Transformation -- 7.5.7.Multistep Transformation -- References -- 8.1.Basic VLSI Switched-Capacitor Circuits -- 8.1.1.Charge Redistribution Analysis Method -- 8.1.2.Noninverted Switched-Capacitor Integrator -- 8.1.3.Inverted Switched-Capacitor Integrator -- 8.1.4.Doubly Pumped Switched-Capacitor Integrator -- 8.2.Basic VLSI SC Circuit Elements -- 8.2.1.VLSI Analog Switch Circuit Structures -- 8.2.2.Nonoverlap Clock-Generation Circuit -- 8.2.3.VLSI OTA Circuit Structures -- 8.3.VLSI Sample/Hold Circuit Structures -- 8.3.1.VLSI Buffered Sample/Hold Circuit -- 8.3.2.Correlated Double Sampling Techniques -- 8.3.3.Nonunity-Gain VLSI SC S/H Circuit -- 8.3.4.Charge Injection Compensation Techniques -- 8.3.5.Fully Differential SC S/H Circuit -- References -- 9.1.Basic VLSI Switched-Current Circuit -- 9.2.Basic VLSI Switched-Current Signal Processing Elements -- 9.2.1.Switched-Current Unity Delay Circuit -- 9.2.2.Switched-Current Adder Circuit -- 9.2.3.Switched-Current Scaling Circuit -- 9.3.VLSI Dynamic Switched-Current-Mirror Structures -- 9.4.Switched-Current Charge Injection Compensation Techniques -- 9.4.1.Charge Injection Attenuation Circuits -- 9.4.2.Charge Injection Cancellation Circuits -- 9.4.3.Algorithmic Charge Cancellation Circuits -- 9.4.4.Full-Differential VLSI SI Circuits -- 9.4.5.Controlled Clocking and Input Techniques -- References -- 10.1.Low-Pass Prototype Filters -- 10.2.Frequency-Scaling Techniques -- 10.2.1.Passive Filters -- 10.2.2.VLSI Active-RC Filters -- 10.2.3.VLSI MOS-C Filters -- 10.2.4.VLSI Gm-C Filters -- 10.2.5.VLSI CTI Filters -- 10.2.6.VLSI SC Filters -- 10.2.7.VLSI SI Filters -- 10.2.8.Filter Pole/Zero under Frequency Scaling -- 10.3.Frequency-Transformation Techniques -- 10.3.1.LP-to-HP Transformation -- 10.3.2.LP-to-BP Transformation -- 10.3.3.LP-to-BS Transformation -- 10.3.4.Hilbert Transform -- References -- 11.1.SFG-Based VLSI Active-RC Filter Design Methods -- 11.1.1.Active-RC Circuit Realization of Integration -- 11.1.2.Active-RC Circuit Realization of Addition -- 11.1.3.Active-RC Circuit Realization of Scaling -- 11.1.4.Design Example -- 11.2.Cascade-Based VLSI Active-RC Filter Design Methods -- 11.2.1.First-Order Active-RC Filter Sections -- 11.2.2.Second-Order Active-RC Filter Sections -- 11.2.3.Low-Pass Filter Sections -- 11.2.4.Band-Pass Filter Sections -- 11.2.5.High-Pass Filter Sections -- 11.3.Sallen-Key Circuits -- 11.3.1.Low-Pass Sallen-Key Circuits -- 11.3.2.High-Pass Sallen-Key Circuits -- 11.3.3.Band-Pass Sallen-Key Circuits -- 11.4.Delyiannis-Friend Circuits -- 11.5.Design Example -- References -- 12.1.SFG-Based VLSI MOS-C Filter Design Methods -- 12.1.1.MOS-C Circuit Realization of Integration -- 12.1.2.MOS-C Circuit Realization of Addition -- 12.1.3.MOS-C Circuit Realization of Scaling -- 12.1.4.Design Example -- 12.2.Cascade-Based VLSI MOS-C Filter Design Methods -- References -- 13.1.SFG-Based VLSI Gm-C Filter Design Methods -- 13.1.1.Gm-C Circuit Realization of Integration -- 13.1.2.Gm-C Circuit Realization of Addition -- 13.1.3.Gm-C Circuit Realization of Scaling -- 13.1.4.Design Example -- 13.2.Cascade-Based VLSI Gm-C Filter Design Methods -- 13.2.1.First-Order Gm-C Filter Sections -- 13.2.2.Second-Order Gm-C Filter Sections -- References -- 14.1.SFG-Based CTI Filter Design Methods -- 14.1.1.CTI Circuit Realization of Integration -- 14.1.2.CTI Circuit Realization of Addition -- 14.1.3.CTI Circuit Realization of Scaling -- 14.1.4.Design Example -- 14.2.Cascade-Based CTI Filter Design Methods -- References -- 15.1.SFG-Based VLSI Oversampling SC Filter Design Methods -- 15.1.1.SC Circuit Realization of Integration -- 15.1.2.SC Circuit Realization of Addition -- 15.1.3.SC Circuit Realization of Scaling -- 15.1.4.Design Example -- 15.2.S-to-Z Transform[—]Based SC Filter Design Methods -- 15.2.1.Design Example -- 15.3.SC Filter Design from Active-RC Circuit Structures -- 15.3.1.Design Example -- 15.4.Exact SFG-Based SC Filter Design Methods -- 15.4.1.Switching Sequence Effect in SC Circuits -- 15.4.2.SC Building Blocks for Exact SC Filter Design -- 15.4.3.Design of Exact SC Filters -- 15.4.4.Design Example -- 15.5.Cascade-Based SC Filter Design Methods -- References -- 16.1.SFG-Based SI Filter Design Methods -- 16.1.1.SI Circuit Realization of Unit Delay -- 16.1.2.SI Circuit Realization of Addition -- 16.1.3.SI Circuit Realization of Scaling -- 16.2.S-to-Z Transform[—]Based SI Filter Design Methods -- 16.2.1.SI Forward Euler Integrator -- 16.2.2.SI Backward Euler Integrator -- 16.3.Cascade-Based SI Filter Design Methods -- 16.4.Design Examples -- References -- 17.1.Mixed-Mode Signal Processing Systems -- 17.2.Basic VLSI V/I and I/V Circuit Structures -- 17.3.Current-Mode-Based Design of Active-RC Filters -- 17.3.1.Current-Mode Active-RC Building Blocks -- 17.3.2.Design Example -- 17.4.Current-Mode-Based Design of Gm-C Filters -- 17.4.1.Current-Mode Gm-C Filter Building Blocks -- 17.4.2.Design Example -- 17.5.Current-Mode-Based Design of SC Filters -- 17.5.1.Current-Mode Building Blocks of SC Filters -- 17.5.2.Design Example -- 17.6.Voltage-Mode-Based Design of CTI Filters -- 17.6.1.Voltage-Mode CTI Filter Building Blocks -- 17.6.2.Design Example -- 17.7.Voltage-Mode-Based Design of SI Filters -- 17.7.1.Voltage-Mode SI Filter Building Blocks -- 17.7.2.Design Example -- References -- 18.1.Active-RC General Impedance Converter Circuits -- 18.1.1.Basic Active-RC GIC Impedance Conversion Rules -- 18.1.2.Active-RC Inductor Simulation -- 18.1.3.Design Example -- 18.2.Gm-C General Impedance Converter Circuits -- 18.2.1.Basic Gm-C GIC Impedance Conversion Rules -- 18.2.2.Gm-C GIC Simulation of Inductors -- 18.2.3.Gm-C Simulation of Resistors -- 18.2.4.Design Example -- 18.3.VLSI Impedance Converter Circuit Structures -- 18.3.1.MOS Cross-Coupled Pair Impedance Converters -- 18.3.2.Single MOS Impedance Converter Circuits -- References -- 19.1.Mixed-Mode Ladder Simulation -- 19.2.Node Voltage-Based Ladder Simulation -- 19.3.VLSI Active Circuit Simulation of All-Pole Ladder Filters -- 19.3.1.Active-RC Circuit Simulation --
Contents note continued: 19.3.2.Gm-C Circuit Simulation -- 19.3.3.CTI Circuit Simulation -- 19.3.4.SC Circuit Simulation -- 19.3.5.SI Circuit Simulation -- 19.4.VLSI Active Circuit Simulation of Band-Pass Ladder Filters -- 19.4.1.Active-RC Circuit Simulation -- 19.4.2.Gm-C Circuit Simulation -- 19.5.Design Examples -- 19.5.1.Active-RC Circuit Simulation -- 19.5.2.Gm-C Circuit Simulation -- 19.5.3.SC Circuit Simulation -- References -- 20.1.Classification of VLSI Filter-Tuning Circuits -- 20.1.1.F-Tuning and Q-Tuning -- 20.1.2.Resistor, Capacitor, and Gm Tuning -- 20.1.3.Direct and Indirect Tuning -- 20.1.4.Closed-Loop and Open-Loop Tuning -- 20.1.5.Continuous and Discrete Tuning -- 20.2.VLSI Analog Filter-Tuning Architectures -- 20.2.1.Single-Slope Tuning -- 20.2.2.Dual-Slope Tuning -- 20.2.3.Phase-Lock Tuning -- 20.2.4.Delay-Response Tuning -- 20.2.5.Gain-Response Tuning -- 20.2.6.Constant-Source/Sink Tuning -- 20.3.VLSI Filter-Tuning Circuits Implementations -- 20.3.1.VLSI Active-RC Filter-Tuning Circuits -- 20.3.2.VLSI MOS-C Filter-Tuning Circuits -- 20.3.3.VLSI Gm-C Filter-Tuning Circuits -- 20.3.4.VLSI CTI Filter-Tuning Circuits -- 20.4.S-Domain Tuning Loops -- 20.4.1.Zero-Pole Tuning Loop -- 20.4.2.Single-Pole Tuning Loop -- 20.4.3.Two-Pole Tuning Loop -- 20.5.Z-Domain Tuning Loops -- 20.5.1.Single-Integrator Tuning Loop -- 20.6.Mixed-Domain Tuning Loops -- References -- 21.1.Design for Robustness -- 21.1.1.Sensitivity Analysis -- 21.1.2.Worst-Case (Corner) Simulations -- 21.1.3.Monte Carlo Simulations -- 21.2.Designs for Low Noise -- 21.2.1.Thermal Noise -- 21.2.2.Shot Noise -- 21.2.3.Low-Frequency (1/f) Noise -- 21.2.4.Noise Bandwidth -- 21.2.5.Modeling of Filter Noise -- 21.3.Designs for High Linearity -- 21.3.1.Harmonic Distortion -- 21.3.2.Intermodulation -- 21.3.3.Filter Nonlinearity Characterization Methods -- References -- 22.1.VLSI Polyphase Filters -- 22.1.1.Hilbert Filters and Hilbert Transform -- 22.1.2.Polyphase Signals -- 22.1.3.Polyphase Filter Transfer Functions -- 22.2.Classic Polyphase Filters -- 22.2.1.Image Rejection Based on Polyphase Filters -- 22.2.2.High-Order Classic Polyphase Filters -- 22.3.Polyphase SFG Representations -- 22.3.1.Polyphase SFG Expression -- 22.3.2.Single-Path Polyphase SFG Expression -- 22.4.Design of VLSI Active Polyphase Filters -- References -- 23.1.VLSI RF Circuit Component Structures -- 23.1.1.VLSI RF Resistor Structures -- 23.1.2.VLSI RF Capacitor Structures -- 23.1.3.VLSI RF Inductor and Transform Structures -- 23.1.4.VLSI RF Varactor Structures -- 23.2.Impedance Transformation and Matching Techniques -- 23.2.1.Impedance Conversion and Matching Network -- 23.2.2.LNA Input Impedance-Matching Circuit -- 23.3.Frequency Translation Techniques -- 23.4.Voltage-Controlled Oscillator (VCO) Circuits -- 23.5.Polyphase Clock Generation Techniques -- 23.6.Distributed Amplifier Circuits -- References -- 24.1.Signal Processing Circuits for SOC Applications -- 24.2.Digital-Based Analog (DBA) Signal Processing Solutions -- 24.2.1.Basic VLSI ASP Functional Elements -- 24.2.2.Basic VLSI Signal Format Conversion Functions -- 24.2.3.Basic VLSI DSP Operations -- 24.2.4.Low-Device-Count Signal Processing Circuits -- 24.3.Design Examples -- 24.3.1.High-Speed I/O Spectral Shaping Tx Circuits -- 24.3.2.TMX I/O Receiver Equalization Circuit -- 24.3.3.Sigma-Delta A/D and D/A Data Conversions -- 24.3.4.Class-D Amplification -- Appendix -- References.

Subject(s):

ISBN:

1259644936 hardcover
9781259644931 hardcover

Note:

Includes index.

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