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Active-HDL 6.3 [electronic resource] : complete FPGA verification environment

Published
Upper Saddle River, N.J. : Pearson/Prentice Hall, [2004]
Copyright Date
©2004
Edition
Version 6.3, student ed.
Physical Description
1 CD-ROM ; 4 3/4 in.

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Summary
This CD offers a completely integrated design entry and verification environment for HDL, C and C++ design. It includes sample designs with training exercises to assist students in learning more about the latest design entry and simulation techniques for the Electronic Design Automation (EDA) industry. Also included are self-paced VHDL and Verilog tutorials.
Subject(s)
ISBN
0131866974
9780131866973
Note
Title from disc label.
Technical Details
System requirements: Pentium PC or higher/compatible microprocessor; 360+ MB spare hard disk memory space; Microsoft WIndows 2000, XP, or NT 4.0 SP6; Microsoft Internet Explorer version 4.0 or higher; 1280 x 1024 monitor resolution.
View MARC record | catkey: 3942142