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Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems / Luigi Pomante

Author
Pomante, Luigi
Published
Gistrup : River Publishers, 2016.
Physical Description
1 online resource
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Contents
Preface xi Acknowledgments xiii -- List of Figures xv -- List of Tables xix -- List of Abbreviations xxi Part 1: System-Level Co-Design of Heterogeneous Multi-Processor Embedded Systems 1 Introduction 3 -- 2 Background 7 -- 2.1 Heterogeneous Multi-Processor Embedded Systems 7 -- 2.1.1 Existing Projects 11 -- 2.1.2 Design Issues 12 -- 2.2 Concurrent HW/SW Design 13 -- 2.2.1 State-of-the-Art 18 -- 2.3 Conclusion 25 -- 3 The Proposed Approach 27 -- 3.1 The Reference Environment: TOSCA 27 -- 3.1.1 The Specification Language 28 -- 3.1.2 Intermediate Representations 29 -- 3.1.3 The Target Architecture 30 -- 3.1.4 Overview of the Design Flow 32 -- 3.2 The Proposed Environment: TOHSCA 39 -- 3.2.1 Target Architecture 44 -- 3.3 Conclusion 46 -- 4 System-Level Co-Specification 47 -- 4.1 System-Level Specification Languages 48 -- 4.2 Reference Language 51 -- 4.2.1 OCCAM 51 -- 4.3 Internal Models 54 -- 4.3.1 Statement-Level Internal Model 55 -- 4.3.2 Procedure-Level Internal Model 57 -- 4.4 Conclusion 60 -- 5 Metrics for Co-Analysis 63 -- 5.1 Characterization 65 -- 5.1.1 GPP Architectural Features 66 -- 5.1.2 DSP Architectural Features 66 -- 5.1.3 ASIC-like Devices Architectural Features 69 -- 5.2 The Proposed Approach 70 -- 5.2.1 Model and Methodology 72 -- 5.2.2 The Tool 81 -- 5.2.3 Validation 82 -- 5.3 Conclusion 83 -- 6 System-Level Co-Estimations 85 -- 6.1 Characterization 87 -- 6.1.1 Performance Estimation 87 -- 6.2 The Proposed Approach 88 -- 6.2.1 Model and Methodology 88 -- 6.2.2 Application of the model to OCCAM2 -- 97 -- 6.2.3 The Tool 117 -- 6.2.4 Validation 119 -- 6.3 Conclusion 122 -- 7 System-Level Partitioning 123 -- 7.1 Characterization 124 -- 7.2 The Proposed Approach 126 -- 7.2.1 Model and Methodology 127 -- 7.2.2 The Tool 134 -- 7.2.3 Validation 135 -- 7.3 Conclusion 138 -- 8 System-Level Co-Simulation 139 -- 8.1 Characterization 141 -- 8.2 The Proposed Approach 142 -- 8.2.1 Model and Methodology 143 -- 8.2.2 The Tool 152 -- 8.2.3 Validation 155 -- 8.3 Conclusion 158. and 9 Case Studies 159 -- 9.1 Case Study 1 -- 159 -- 9.1.1 Co-specification 159 -- 9.1.2 Co-analysis 160 -- 9.1.3 Co-estimation 161 -- 9.1.4 Functional Co-simulation 162 -- 9.1.5 Load Estimation 163 -- 9.1.6 System Design Exploration 163 -- 9.1.7 Toward the Low-level Co-design Flow 165 -- 9.2 Case Study 2 -- 165 -- 9.2.1 Co-specification 166 -- 9.2.2 Co-analysis 166 -- 9.2.3 Co-estimation 167 -- 9.2.4 Functional Co-simulation 167 -- 9.2.5 Load Estimation 168 -- 9.2.6 System Design Exploration 168 -- 9.2.7 Toward a Low-level Co-design Flow 170 -- 9.3 Conclusion 170 Conclusions (Part 1) 171 Part 2 -- 10 System-Level Design Space Exploration 175 -- 10.1 Introduction 175 -- 10.2 Reference Co-Design Flow 177 -- 10.3 Specification 181 -- 10.4 Target HWArchitecture 185 -- 10.5 Design Space Exploration 187 -- 10.5.1 First Phase 187 -- 10.5.2 Second Phase 192 -- 10.5.3 Illustrative Example 195 -- 10.6 Conclusion 198 -- 11 SystemC-Based ESL Design Space Exploration 199 -- 11.1 Introduction 199 -- 11.2 Reference ESL HW/SW Co-Design Flow 201 -- 11.2.1 System Behavior Model 201 -- 11.2.2 Technologies Library 203 -- 11.2.3 Functional Simulation 203 -- 11.2.4 Co-Analysis and Co-Estimation 204 -- 11.2.5 Design Space Exploration 204 -- 11.2.6 Algorithm-Level Flow 205 -- 11.2.7 Reference Template HWArchitecture 205 -- 11.3 SystemC-Based ESL HW/SW Co-Design Environment 206 -- 11.3.1 System Behavior Model 206 -- 11.3.2 Functional Simulation 207 -- 11.3.3 Co-Analysis and Co-Estimation 207 -- 11.3.4 Design Space Exploration 208 -- 11.4 SystemC-Based ESL Design Space Exploration 208 -- 11.4.1 HW/SW Partitioning, Mapping, and Architecture Definition (1st Phase) 209 -- 11.4.1.1 Inputs modeling 210 -- 11.4.1.2 Technologies library modeling 211 -- 11.4.1.3 PAM specification modeling 211 -- 11.4.1.4 Optimization engine, individuals, and allocation modeling 213 -- 11.4.2 Timing Co-Simulation 213 -- 11.5 FIR-FIR-GCD Case Study 216 -- 11.6 Conclusion 222 -- References 223 -- Index 239 About the Author 245.
Summary
Modern electronic systems consist of a fairly heterogeneous set of components. Today, a single system can be constituted by a hardware platform, frequently composed of a mix of analog and digital components, and by several software application layers. The hardware can include several heterogeneous microprocessors (e.g. GPP, DSP, GPU, etc.), dedicated ICs (ASICs and/or FPGAs), memories, a set of local connections between the system components, and some interfaces between the system and the environment (sensors, actuators, etc.). Therefore, on the one hand, multi-processor embedded systems are capable of meeting the demand of processing power and flexibility of complex applications. On the other hand, such systems are very complex to design and optimize, so that the design methodology plays a major role in determining the success of the products. For these reasons, to cope with the increasing system complexity, the approaches typically used today are oriented towards co-design methodologies working at the higher levels of abstraction. Unfortunately, such methodologies are typically customized for the specific application, suffer of a lack of generality and still need a considerable effort when real-size project are envisioned. Therefore, there is still the need for a general methodology able to support the designer during the high-level steps of a co-design flow, enabling an effective design space exploration before tackling the low-level steps and thus committing to the final technology. This should prevent costly redesign loops.In such a context, the work described in this book, composed of two parts, aims at providing models, methodologies and tools to support each step of the co-design flow of embedded systems implemented by exploiting heterogeneous multi-processor architectures mapped on distributed systems, as well as fully integrated onto a single chip. The first part focuses on issues like the analysis of system specification languages, and the analysis of existing system-level HW/SW co-simulation methodologies to support heterogeneous multi-processor architectures. The second part focuses mainly on Design Space Exploration, and it presents both some theoretical advancements with respect to the first part, and the development of a prototypal framework that provides practical exploitation of the proposed concepts.
Subject(s)
ISBN
9788793379374 (e-book)
8793379374
9788793379381
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