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Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia

Author
Bellido, Manuel J., 1964-
Published
London : Imperial College Press, [2006]
Copyright Date
©2006
Physical Description
1 online resource (xvii, 267 pages) : illustrations
Additional Creators
Juan Chico, Jorge and Valencia, Manuel
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Contents
Machine generated contents note: 1. Fundamentals of timing simulation -- 2. Delay models : evolution and trends -- 3. Degradation and inertial effects -- 4. CMOS inverter degradation delay model -- 5. Gate-level DDM -- 6. Logic level simulator design and implementation -- 7. DDM simulation results.
Summary
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl
Subject(s)
ISBN
1860945899
9781860945892
1860947360 (electronic bk.)
9781860947360 (electronic bk.)
Digital File Characteristics
data file
Bibliography Note
Includes bibliographical references and index.
View MARC record | catkey: 43227974