This report describes logic programming approaches to two graph theoretical problems relevant to reactor and logic circuit analysis: those of cutset verification and subsystem detection. In a graph representation of a system involving components and their interconnections, sets of arcs that divide the graph into two disconnected subgraphs are termed cutsets. Two Prolog programs have been developed. The first verifies that a given cutset is, indeed, a cutset (i.e., that there are no sneak paths between the two subgraphs maintaining connectivity). The second detects possible subsystems of a device, thus simplifying the task of fault diagnosis.