Circuit design and simulation with VHDL / Volnei A. Pedroni
- Author:
- Pedroni, Volnei A.
- Published:
- Cambridge, Mass. : MIT Press, [2010]
- Copyright Date:
- ©2010
- Edition:
- 2nd ed.
- Physical Description:
- xix, 608 pages : illustrations ; 24 cm
- Additional Creators:
- Pedroni, Volnei A.
- Contents:
- I. CIRCUIT-LEVEL VHDL -- 1. Introduction -- 1.1. About VHDL -- 1.2. VHDL Versions -- 1.3. Design Flow -- 1.4. EDA Tools -- 1.5. Translation of VHDL Code into a Circuit -- 1.6. Circuit Simulation -- 1.7. VHDL Syntax -- 1.8. Number and Character Representations in VHDL -- 2. Code Structure -- 2.1. Fundamental VHDL Units -- 2.2. VHDL Libraries and Packages -- 2.3. Library/Package Declarations -- 2.4. Entity -- 2.5. Architecture -- 2.6. Generic -- 2.7. Introductory VHDL Examples -- 2.8. Coding Guidelines -- 2.9. VHDL 2008 -- 2.10. Exercises -- 3. Data Types -- 3.1. Introduction -- 3.2. VHDL Objects -- 3.3. Data-Type Libraries and Packages -- 3.4. Type Classifications -- 3.5. Standard Data Types -- 3.6. Standard-Logic Data Types -- 3.7. Unsigned and Signed Data Types -- 3.8. Fixed-and Floating-Point Types -- 3.9. Predefined Data Types Summary -- 3.10. User-Defined Scalar Types -- 3.11. User-Defined Array Types -- 3.12. Integer versus Enumerated Indexing -- 3.13. Array Slicing -- 3.14. Records -- 3.15. Subtypes -- 3.16. Specifying PORT Arrays -- 3.17. Qualified Types and Overloading -- 3.18. Type Conversion -- 3.19. Legal versus Illegal Assignments -- 3.20. Access Types -- 3.21. File Types -- 3.22. VHDL 2008 -- 3.23. Exercises -- 4. Operators and Attributes -- 4.1. Introduction -- 4.2. Predefined Operators -- 4.3. Overloaded and User-Defined Operators -- 4.4. Predefined Attributes -- 4.5. User-Defined Attributes -- 4.6. Synthesis Attributes -- 4.7. Group -- 4.8. Alias -- 4.9. VHDL 2008 -- 4.10. Exercises -- 5. Concurrent Code -- 5.1. Introduction -- 5.2. Using Operators -- 5.3. The When Statement -- 5.4. The Select Statement -- 5.5. The Generate Statement -- 5.6. Implementing Sequential Circuits with Concurrent Code -- 5.7. Implementing Arithmetic Circuits with Operators -- 5.8. Preventing Combinational-Logic Simplification -- 5.9. Allowing Multiple Signal Assignments -- 5.10. VHDL 2008 -- 5.11. Exercises -- 6. Sequential Code -- 6.1. Introduction -- 6.2. Latches and Flip-flops -- 6.3. Process -- 6.4. The IF Statement -- 6.5. The WAIT Statement -- 6.6. The Loop Statement -- 6.7. The Case Statement -- 6.8. Case versus Select -- 6.9. Implementing Combinational Circuits with Sequential Code -- 6.10. VHDL 2008 -- 6.11. Exercises -- 7. Signal and Variable -- 7.1. Introduction -- 7.2. Signal -- 7.3. Variable -- 7.4. Signal versus Variable -- 7.5. The Inference of Registers -- 7.6. Dual-Edge Circuits -- 7.7. Making Multiple Signal Assignments -- 7.8. Exercises -- II. SYSTEM-LEVEL VHDL -- 8. Package and Component -- 8.1. Introduction -- 8.2. Package -- 8.3. Component -- 8.4. Generic Map -- 8.5. Component Instantiation with Generate -- 8.6. Configuration -- 8.7. Block -- 8.8. VHDL 2008 -- 8.9. Exercises -- 9. Function and Procedure -- 9.1. Introduction -- 9.2. The Assert Statement -- 9.3. Function -- 9.4. Procedure -- 9.5. Function versus Procedure Summary -- 9.6. Overloading -- 9.7. VHDL 2008 -- 9.8. Exercises -- 10. Simulation with VHDL Testbenches -- 10.1. Introduction -- 10.2. Simulation Types -- 10.3. Writing Data to Files -- 10.4. Reading Data From Files -- 10.5. Graphical Simulation (Preparing the Design) -- 10.6. Stimulus Generation -- 10.7. General VHDL Template for Testbenches -- 10.8. Type I Testbench (Manual Functional Simulation) -- 10.9. Type II Testbench (Manual Timing Simulation) -- 10.10. Type III Testbench (Automated Functional Simulation) -- 10.11. Type IV Testbench (Automated Timing Simulation) -- 10.12. Testbenches with Record Types -- 10.13. Testbenches with Data Files -- 10.14. Exercises -- III. EXTENDED AND ADVANCED DESIGNS -- 11. VHDL Design of State Machines -- 11.1. Introduction -- 11.2. VHDL Template for FSMs -- 11.3. Poor FSM Model -- 11.4. FSM Encoding Styles -- 11.5. The State-Bypass Problem in FSMs -- 11.6. Systematic Design Technique for Timed Machines -- 11.7. FSMs with Repetitive States -- 11.8. Other FSM Designs -- 11.9. Exercises -- 12. VHDL Design with Basic Displays -- 12.1. Introduction -- 12.2. Basic LED/SSD/LCD Driver -- 12.3. Playing with a Seven-Segment Display -- 12.4. Frequency Meter (with LCD) -- 12.5. Digital Clock (With SSDs) -- 12.6. Quick-Finger Game (With LEDs and SSDs) -- 12.7. Other Designs with Basic Displays -- 12.8. Exercises -- 13. VHDL Design of Memory Circuits -- 13.1. Introduction -- 13.2. Implementing Bidirectional Buses -- 13.3. Memory Initialization Files -- 13.4. ROM Design -- 13.5. RAM Design -- 13.6. External Memory Interfaces -- 13.7. Exercises -- 14. VHDL Design of Serial Communication Circuits -- 14.1. Introduction -- 14.2. Data Serializers/Deserializers -- 14.3. PS2 Interface -- 14.4. I2C Interface -- 14.5. SPI Interface -- 14.6. TMDS Interface -- 14.7. Video Interfaces: VGA, DVI, and FPD-Link -- 14.8. Exercises -- 15. VHDL Design of VGA Video Interfaces -- 15.1. Introduction -- 15.2. VGA Connector -- 15.3. DDC and EDID -- 15.4. Circuit Diagram -- 15.5. Control Signals -- 15.6. Pixel Signals -- 15.7. Setup for the Experiments -- 15.8. Comments on VHDL Code for VGA Systems -- 15.9. Hardware-Generated Image -- 15.10. Image Generation with a File and On-Chip Memory -- 15.11. Arbitrary Image Generation with a File and Off-Chip Memory -- 15.12. Image Equalization with Gamma Expansion -- 15.13. Exercises -- 16. VHDL Design of DVI Video Interfaces -- 16.1. Introduction -- 16.2. Circuit Diagram -- 16.3. Display Resolutions -- 16.4. DVI Types and DVI Connectors -- 16.5. DVI versus HDMI -- 16.6. Setup for the Experiments -- 16.7. Hardware-Generated Image -- 16.8. Other DVI Designs -- 16.9. Exercises -- 17. VHDL Design of FPD-Link Video Interfaces -- 17.1. Introduction -- 17.2. FPD-Link Encoder -- 17.3. Setup for the Experiments -- 17.4. Hardware-Generated Image -- 17.5. Hardware-Generated Image with Characters -- 17.6. Other Designs -- 17.7. Exercises -- APPENDICES -- A. Programmable Logic Devices -- B. Altera Quartus II Tutorial -- C. Xilinx ISE Tutorial -- D. ModelSim Tutorial -- E. Altera DE2 Board Tutorial -- F. BMP-to-RAW File Converter Tutorial -- G. Using Macrofunctions -- H. Package standard (2002 and 2008) -- I. Package stdl̲ogic1̲164 (1993 and 2008) -- J. Package numerics̲td (1997 and 2008) -- K. Package stdl̲ogica̲rith -- L. Package stdl̲ogics̲igned -- M. Package textio (2002 and 2008) -- N. Package numerics̲tdu̲nsigned (2008) -- O. Reserved Words in VHDL 2008.
- Subject(s):
- ISBN:
- 9780262014335 (hardcover : alk. paper)
0262014335 (hardcover : alk. paper) - Note:
- Rev. ed. of: Circuit design with VHDL / Volnei A. Pedroni. 2004.
- Bibliography Note:
- Includes bibliographical references and index.
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