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Designing asynchronous circuits using NULL convention logic (NCL) [electronic resource] / Scott C. Smith and Jia Di.

Author
Smith, Scott C.
Published
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, [2009]
Copyright Date
©2009
Physical Description
1 electronic text (x, 86 pages : illustrations) : digital file
Additional Creators
Di, Jia
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Restrictions on Access
Abstract freely available; full-text restricted to subscribers or individual document purchasers.
Contents
Introduction to asynchronous logic -- Overview of NULL convention logic (NCL) -- NCL system framework and fundamental components -- Transistor-level NCL gate design -- Combinational NCL circuit design -- Input-completeness and observability -- Dual-rail NCL design -- Quad-rail NCL design -- Sequential NCL circuit design -- NCL implementation of Mealy and Moore machines -- NCL implementation of algorithmic state machines -- NCL throughput optimization -- Pipelining -- Embedded registration -- Early completion -- NULL cycle reduction -- Low-power NCL design -- Wavefront steering -- Multi-threshold CMOS (MTCMOS) for NCL (MTNCL) -- MTCMOS for synchronous circuits -- Implementing MTCMOS in NCL circuits -- Comprehensive NCL design example.
Summary
Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power.
Subject(s)
ISBN
9781598299823 (electronic bk.)
9781598299816 (pbk.)
Related Titles
Synthesis digital library of engineering and computer science
Note
Part of: Synthesis digital library of engineering and computer science.
Title from PDF t.p. (viewed on August 9, 2009).
Series from website.
Bibliography Note
Includes bibliographical references.
Other Forms
Also available in print.
Technical Details
Mode of access: World Wide Web.
System requirements: Adobe Acrobat reader.
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View MARC record | catkey: 7058498