RF circuit design / Richard Chi Hsi Li.
- Author
- Li, Richard Chi-Hsi, 1938-
- Published
- Hoboken, New Jersey : John Wiley & Sons, Inc., [2012]
- Copyright Date
- ©2012
- Edition
- Second edition.
- Physical Description
- xx, 840 pages : illustrations ; 27 cm.
- Series
- Contents
- Machine generated contents note: 1.Difference Between RF And Digital Circuit Design -- 1.1.Controversy -- 1.1.1.Impedance Matching -- 1.1.2.Key Parameter -- 1.1.3.Circuit Testing and Main Test Equipment -- 1.2.Difference of RF and Digital Block in a Communication System -- 1.2.1.Impedance -- 1.2.2.Current Drain -- 1.2.3.Location -- 1.3.Conclusions -- 1.4.Notes for High-Speed Digital Circuit Design -- Further Reading -- Exercises -- Answers -- 2.Reflection And Self-Interference -- 2.1.Introduction -- 2.2.Voltage Delivered from a Source to a Load -- 2.2.1.General Expression of Voltage Delivered from a Source to a Load when l << λ4 so that Td -> 0 -- 2.2.2.Additional Jitter or Distortion in a Digital Circuit Block -- 2.3.Power Delivered from a Source to a Load -- 2.3.1.General Expression of Power Delivered from a Source to a Load when l << λ/4 so that Td -> 0 -- 2.3.2.Power Instability -- 2.3.3.Additional Power Loss -- 2.3.4.Additional Distortion -- 2.3.5.Additional Interference -- 2.4.Impedance Conjugate Matching -- 2.4.1.Maximizing Power Transport -- 2.4.2.Power Transport without Phase Shift -- 2.4.3.Impedance Matching Network -- 2.4.4.Necessity of Impedance Matching -- 2.5.Additional Effect of Impedance Matching -- 2.5.1.Voltage Pumped up by Means of Impedance Matching -- 2.5.2.Power Measurement -- Appendices -- 2.A.1.VSWR and Other Reflection and Transmission Coefficients -- 2.A.2.Relationships between Power (dBm), Voltage (V), and Power (W) -- Reference -- Further Reading -- Exercises -- Answers -- 3.Impedance Matching In The Narrow-Band Case -- 3.1.Introduction -- 3.2.Impedance Matching by Means of Return Loss Adjustment -- 3.2.1.Return Loss Circles on the Smith Chart -- 3.2.2.Relationship between Return Loss and Impedance Matching -- 3.2.3.Implementation of an Impedance Matching Network -- 3.3.Impedance Matching Network Built by One Part -- 3.3.1.One Part Inserted into Impedance Matching Network in Series -- 3.3.2.One Part Inserted into the Impedance Matching Network in Parallel -- 3.4.Impedance Matching Network Built by Two Parts -- 3.4.1.Regions in a Smith Chart -- 3.4.2.Values of Parts -- 3.4.3.Selection of Topology -- 3.5.Impedance Matching Network Built By Three Parts -- 3.5.1."Π" Type and "T" Type Topologies -- 3.5.2.Recommended Topology -- 3.6.Impedance Matching When ZS Or ZL Is Not 50 Ω -- 3.7.Parts In An Impedance Matching Network -- Appendices -- 3.A.1.Fundamentals of the Smith Chart -- 3.A.2.Formula for Two-Part Impedance Matching Network -- 3.A.3.Topology Limitations of the Two-Part Impedance Matching Network -- 3.A.4.Topology Limitation of Three Parts Impedance Matching Network -- 3.A.5.Conversion between Π and T Type Matching Network -- 3.A.6.Possible Π and T Impedance Matching Networks -- Reference -- Further Reading -- Exercises -- Answers -- 4.Impedance Matching In The Wideband Case -- 4.1.Appearance of Narrow and Wideband Return Loss on a Smith Chart -- 4.2.Impedance Variation Due to the Insertion of One Part Per Arm or Per Branch -- 4.2.1.An Inductor Inserted into Impedance Matching Network in Series -- 4.2.2.A Capacitor Inserted into Impedance Matching Network in Series -- 4.2.3.An Inductor Inserted into Impedance Matching Network in Parallel -- 4.2.4.A Capacitor Inserted into Impedance Matching Network in Parallel -- 4.3.Impedance Variation Due to the Insertion of Two Parts Per Arm or Per Branch -- 4.3.1.Two Parts Connected in Series to Form One Arm -- 4.3.2.Two Parts Are Connected in Parallel to Form One Branch -- 4.4.Partial Impedance Matching for an IQ (in Phase Quadrature) Modulator in a UWB (Ultra Wide Band) System -- 4.4.1.Gilbert Cell -- 4.4.2.Impedances of the Gilbert Cell -- 4.4.3.Impedance Matching for LO, RF, and IF Ports Ignoring the Bandwidth -- 4.4.4.Wide Bandwidth Required in a UWB (Ultra Wide Band) System -- 4.4.5.Basic Idea to Expand the Bandwidth -- 4.4.6.Example 1: Impedance Matching in IQ Modulator Design for Group 1 in a UWB System -- 4.4.7.Example 2: Impedance Matching in IQ Modulator Design for Group 3 + Group 6 in a UWB System -- 4.5.Discussion of Passive Wideband Impedance Matching Network -- 4.5.1.Impedance Matching for the Gate of a MOSFET Device -- 4.5.2.Impedance Matching for the Drain of a MOSFET Device -- Further Reading -- Exercises -- Answers -- 5.Impedance And Gain Of A Raw Device -- 5.1.Introduction -- 5.2.Miller Effect -- 5.3.Small-Signal Model of a Bipolar Transistor -- 5.4.Bipolar Transistor with CE (Common Emitter) Configuration -- 5.4.1.Open-Circuit Voltage Gain AvCE of a CE Device -- 5.4.2.Short-Circuit Current Gain βCE and Frequency Response of a CE Device -- 5.4.3.Primary Input and Output Impedance of a CE (common emitter) device -- 5.4.4.Miller's Effect in a Bipolar Transistor with CE Configuration -- 5.4.5.Emitter Degeneration -- 5.5.Bipolar Transistor with CB (Common Base) Configuration -- 5.5.1.Open-Circuit Voltage Gain AvCB of a CB Device -- 5.5.2.Short-Circuit Current Gain βCG and Frequency Response of a CB Device -- 5.5.3.Input and Output Impedance of a CB Device -- 5.6.Bipolar Transistor with CC (Common Collector) Configuration -- 5.6.1.Open-Circuit Voltage Gain AvCC of a CC Device -- 5.6.2.Short-Circuit Current Gain βCG and Frequency Response of the Bipolar Transistor with CC Configuration -- 5.6.3.Input and Output Impedance of a CC Device -- 5.7.Small-Signal Model of a MOSFET -- 5.8.Similarity Between a Bipolar Transistor and a MOSFET -- 5.8.1.Simplified Model of CS Device -- 5.8.2.Simplified Model of CG Device -- 5.8.3.Simplified Model of CD Device -- 5.9.MOSFET with CS (Common Source) Configuration -- 5.9.1.Open-Circuit Voltage Gain AvCS of a CS Device -- 5.9.2.Short-Circuit Current Gain βCS and Frequency Response of a CS Device -- 5.9.3.Input and Output Impedance of a CS Device -- 5.9.4.Source Degeneration -- 5.10.MOSFET with CG (Common Gate) Configuration -- 5.10.1.Open-Circuit Voltage Gain of a CG Device -- 5.10.2.Short-Circuit Current Gain and Frequency Response of a CG Device -- 5.10.3.Input and Output Impedance of a CG Device -- 5.11.MOSFET with CD (Common Drain) Configuration -- 5.11.1.Open-Circuit Voltage Gain AvCD of a CD Device -- 5.11.2.Short-Circuit Current Gain βCD and Frequency Response of a CD Device -- 5.11.3.Input and Output Impedance of a CD Device -- 5.12.Comparison of Transistor Configuration of Single-stage Amplifiers with Different Configurations -- Further Reading -- Exercises -- Answers -- 6.Impedance Measurement -- 6.1.Introduction -- 6.2.Scalar and Vector Voltage Measurement -- 6.2.1.Voltage Measurement by Oscilloscope -- 6.2.2.Voltage Measurement by Vector Voltmeter -- 6.3.Direct Impedance Measurement by a Network Analyzer -- 6.3.1.Direction of Impedance Measurement -- 6.3.2.Advantage of Measuring S Parameters -- 6.3.3.Theoretical Background of Impedance Measurement by S Parameters -- 6.3.4.S Parameter Measurement by Vector Voltmeter -- 6.3.5.Calibration of the Network Analyzer -- 6.4.Alternative Impedance Measurement by Network Analyzer -- 6.4.1.Accuracy of the Smith Chart -- 6.4.2.Low- and High-Impedance Measurement -- 6.5.Impedance Measurement Using a Circulator -- Appendices -- 6.A.1.Relationship Between the Impedance in Series and in Parallel -- Further Reading -- Exercises -- Answers -- 7.Grounding -- 7.1.Implication of Grounding -- 7.2.Possible Grounding Problems Hidden in a Schematic -- 7.3.Imperfect or Inappropriate Grounding Examples -- 7.3.1.Inappropriate Selection of Bypass Capacitor -- 7.3.2.Imperfect Grounding -- 7.3.3.Improper Connection -- 7.4.'Zero' Capacitor -- 7.4.1.What is a Zero Capacitor -- 7.4.2.Selection of a Zero Capacitor -- 7.4.3.Bandwidth of a Zero Capacitor -- 7.4.4.Combined Effect of Multi-Zero Capacitors -- 7.4.5.Chip Inductor is a Good Assistant -- 7.4.6.Zero Capacitor in RFIC Design -- 7.5.Quarter Wavelength of Microstrip Line -- 7.5.1.A Runner is a Part in RF Circuitry -- 7.5.2.Why Quarter Wavelength is so Important -- 7.5.3.Magic Open-Circuited Quarter Wavelength of Microstrip Line -- 7.5.4.Testing for Width of Microstrip Line with Specific Characteristic Impedance -- 7.5.5.Testing for Quarter Wavelength -- Appendices -- 7.A.1.Characterizing of Chip Capacitor and Chip Inductor by Means of S21 Testing -- 7.A.2.Characterizing of Chip Resistor by Means of S11 of S22 Testing -- Reference -- Further Reading -- Exercises -- Answers -- 8.Equipotentiality And Current Coupling On The Ground Surface -- 8.1.Equipotentiality on the Ground Surface -- 8.1.1.Equipotentiality on the Grounded Surface of an RF Cable -- 8.1.2.Equipotentiality on the Grounded Surface of a PCB -- 8.1.3.Possible Problems of a Large Test PCB -- 8.1.4.Coercing Grounding -- 8.1.5.Testing for Equipotentiality -- 8.2.Forward and Return Current Coupling -- 8.2.1.Indifferent Assumption and Great Ignore -- 8.2.2.Reduction of Current Coupling on a PCB -- 8.2.3.Reduction of Current Coupling in an IC Die -- 8.2.4.Reduction of Current Coupling between Multiple RF Blocks -- 8.2.5.A Plausible System Assembly -- 8.3.PCB or IC Chip with Multimetallic Layers -- Further Reading -- Exercises -- Answers -- 9.Layout -- 9.1.Difference in Layout between an Individual Block and a System -- 9.2.Primary Considerations of a PCB -- 9.2.1.Types of PCBs -- 9.2.2.Main Electromagnetic Parameters -- 9.2.3.Size -- 9.2.4.Number of Metallic Layers -- 9.3.Layout of a PCB for Testing -- 9.4.VIA Modeling -- 9.4.1.Single Via -- 9.4.2.Multivias -- 9.5.Runner -- 9.5.1.When a Runner is Connected with the Load in Series -- 9.5.2.When a Runner is Connected to the Load in Parallel -- 9.5.3.Style of Runner -- 9.6.Parts -- 9.6.1.Device -- 9.6.2.Inductor -- 9.6.3.Resistor -- 9.6.4.Capacitor -- 9.7.Free Space -- References -- Further Reading -- Exercises -- Answers -- 10.Manufacturability Of Product Design -- 10.1.Introduction -- 10.2.Implication of 6σ Design -- 10.2.1.6σ and Yield Rate -- 10.2.2.6σ Design for a Circuit Block -- and Contents note continued: 10.2.3.6σ Design for a Circuit System -- 10.3.Approaching 6σ Design -- 10.3.1.By Changing of Parts' σ Value -- 10.3.2.By Replacing Single Part with Multiple Parts -- 10.4.Monte Carlo Analysis -- 10.4.1.A Band-Pass Filter -- 10.4.2.Simulation with Monte Carlo Analysis -- 10.4.3.Sensitivity of Parts on the Parameter of Performance -- Appendices -- 10.A.1.Fundamentals of Random Process -- 10.A.2.Index Cp and Cpk Applied in 6σ Design -- 10.A.3.Table of the Normal Distribution -- Further Reading -- Exercises -- Answers -- 11.RFIC (Radio Frequency Integrated Circuit) -- 11.1.Interference and Isolation -- 11.1.1.Existence of Interference in Circuitry -- 11.1.2.Definition and Measurement of Isolation -- 11.1.3.Main Path of Interference in a RF Module -- 11.1.4.Main Path of Interference in an IC Die -- 11.2.Shielding for an RF Module by a Metallic Shielding Box -- 11.3.Strong Desirability to Develop RFIC -- 11.4.Interference going along IC Substrate Path -- 11.4.1.Experiment -- 11.4.2.Trench -- 11.4.3.Guard Ring -- 11.5.Solution for Interference Coming from Sky -- 11.6.Common Grounding Rules for RF Module and RFIC Design -- 11.6.1.Grounding of Circuit Branches or Blocks in Parallel -- 11.6.2.DC Power Supply to Circuit Branches or Blocks in Parallel -- 11.7.Bottlenecks in RFIC Design -- 11.7.1.Low-Q Inductor and Possible Solution -- 11.7.2."Zero" Capacitor -- 11.7.3.Bonding Wire -- 11.7.4.Via -- 11.8.Calculating of Quarter Wavelength -- Reference -- Further Reading -- Exercises -- Answers -- 12.Main Parameters And System Analysis In RF Circuit Design -- 12.1.Introduction -- 12.2.Power Gain -- 12.2.1.Basic Concept of Reflection Power Gain -- 12.2.2.Transducer Power Gain -- 12.2.3.Power Gain in a Unilateral Case -- 12.2.4.Power Gain in a Unilateral and Impedance-Matched Case -- 12.2.5.Power Gain and Voltage Gain -- 12.2.6.Cascaded Equations of Power Gain -- 12.3.Noise -- 12.3.1.Significance of Noise Figure -- 12.3.2.Noise Figure in a Noisy Two-Port RF Block -- 12.3.3.Notes on Noise Figure Testing -- 12.3.4.An Experimental Method to Obtain Noise Parameters -- 12.3.5.Cascaded Equations of Noise Figure -- 12.3.6.Sensitivity of a Receiver -- 12.4.Nonlinearity -- 12.4.1.Nonlinearity of a Device -- 12.4.2.IP (Intercept Point) and IMR (Intermodulation Rejection) -- 12.4.3.Cascaded Equations of Intercept Point -- 12.4.4.Nonlinearity and Distortion -- 12.5.Other Parameters -- 12.5.1.Power Supply Voltage and Current Drain -- 12.5.2.Part Count -- 12.6.Example of RF System Analysis -- Appendices -- 12.A.1.Conversion between Watts, Volts, and dBm, in a System with 50 Ω Input and Output Impedance -- 12.A.2.Relationship between voltage reflection coefficient, Γ, and Transmission coefficients when the load R[„] is equal to the standard characteristic resistance, 50 Ω) -- 12.A.3.Definition of Powers in a Two-Port Block by Signal Flow Graph -- 12.A.4.Main Noise Sources -- References -- Further Reading -- Exercises -- Answers -- 13.Speciality of "Zero If" System -- 13.1.Why Differential Pair? -- 13.1.1.Superficial Difference between Single-Ended and Differential Pair -- 13.1.2.Nonlinearity in Single-Ended Stage -- 13.1.3.Nonlinearity in a Differential Pair -- 13.1.4.Importance of Differential Configuration in a Direct Conversion or Zero IF Communication System -- 13.1.5.Why Direct Conversion or Zero IF? -- 13.2.Can DC Offset be Blocked out by a Capacitor? -- 13.3.Chopping Mixer -- 13.4.DC Offset Cancellation by Calibration -- 13.5.Remark on DC Offset Cancellation -- Further Reading -- Exercises -- Answers -- 14.Differential Pairs -- 14.1.Fundamentals of Differential Pairs -- 14.1.1.Topology and Definition of a Differential Pair -- 14.1.2.Transfer Characteristic of a Bipolar Differential Pair -- 14.1.3.Small Signal Approximation of a Bipolar Differential Pair -- 14.1.4.Transfer Characteristic of a MOSFET Differential Pair -- 14.1.5.Small Signal Approximation of a MOSFET Differential Pair -- 14.1.6.What Happens If Input Signal Is Imperfect Differential -- 14.2.CMRR (Common Mode Rejection Ratio) -- 14.2.1.Expression of CMRR -- 14.2.2.CMRR in a Single-Ended Stage -- 14.2.3.CMRR in a Pseudo-Differential Pair -- 14.2.4.Enhancement of CMRR -- Reference -- Further Reading -- Exercises -- Answers -- 15.RF Balun -- 15.1.Introduction -- 15.2.Transformer Balun -- 15.2.1.Transformer Balun in RF Circuit Design with Discrete Parts -- 15.2.2.Transformer Balun in RFIC Design -- 15.2.3.An Ideal Transformer Balun for Simulation -- 15.2.4.Equivalence of Parts between Single-Ended and Differential Pair in Respect to an Ideal Transformer Balun -- 15.2.5.Impedance Matching for Differential Pair by means of Transformer Balun -- 15.3.LC Balun -- 15.3.1.Simplicity of LC Balun Design -- 15.3.2.Performance of a Simple LC Balun -- 15.3.3.A Practical LC Balun -- 15.4.Microstrip Line Balun -- 15.4.1.Ring Balun -- 15.4.2.Split Ring Balun -- 15.5.Mixing Type of Balun -- 15.5.1.Balun Built by Microstrip Line and Chip Capacitor -- 15.5.2.Balun Built by Chip Inductors and Chip Capacitors -- Appendices -- 15.A.1.Transformer Balun Built by Two Stacked Transformers -- 15.A.2.Analysis of a Simple LC Balun -- 15.A.3.Example of Calculating of L and C Values for a Simple LC Balun -- 15.A.4.Equivalence of Parts between Single-Ended and Differential Pair with Respect to a Simple LC Balun -- 15.A.5.Some Useful Couplers -- 15.A.6.Cable Balun -- Reference -- Further Reading -- Exercises -- Answers -- 16.SOC (System-On-A-Chip) And Next -- 16.1.SOC -- 16.1.1.Basic Concept -- 16.1.2.Remove Bottlenecks in Approach to RFIC -- 16.1.3.Study Isolation between RFIC, Digital IC, and Analog IC -- 16.2.What is Next -- Appendices -- 16.A.1.Packaging -- References -- Further Reading -- Exercises -- Answers -- 17.LNA (Low-Noise Amplifier) -- 17.1.Introduction -- 17.2.Single-Ended Single Device LNA -- 17.2.1.Size of Device -- 17.2.2.Raw Device Setup and Testing -- 17.2.3.Challenge for a Good LNA Design -- 17.2.4.Input and Output Impedance Matching -- 17.2.5.Gain Circles and Noise Figure Circles -- 17.2.6.Stability -- 17.2.7.Nonlinearity -- 17.2.8.Design Procedures -- 17.2.9.Other Examples -- 17.3.Single-Ended Cascode LNA -- 17.3.1.Bipolar CE-CB Cascode Voltage Amplifier -- 17.3.2.MOSFET CS-CG Cascode Voltage Amplifier -- 17.3.3.Why Cascode? -- 17.3.4.Example -- 17.4.LNA with AGC (Automatic Gain Control) -- 17.4.1.AGC Operation -- 17.4.2.Traditional LNA with AGC -- 17.4.3.Increase in AGC Dynamic Range -- 17.4.4.Example -- References -- Further Reading -- Exercises -- Answers -- 18.Mixer -- 18.1.Introduction -- 18.2.Passive Mixer -- 18.2.1.Simplest Passive Mixer -- 18.2.2.Double-Balanced Quad-Diode Mixer -- 18.2.3.Double-Balanced Resistive Mixer -- 18.3.Active Mixer -- 18.3.1.Single-End Single Device Active Mixer -- 18.3.2.Gilbert Cell -- 18.3.3.Active Mixer with Bipolar Gilbert Cell -- 18.3.4.Active Mixer with MOSFET Gilbert Cell -- 18.4.Design Schemes -- 18.4.1.Impedance Measuring and Matching -- 18.4.2.Current Bleeding -- 18.4.3.Multi-tanh Technique -- 18.4.4.Input Types -- Appendices -- 18.A.1.Trigonometric and Hyperbolic Functions -- 18.A.2.Implementation of tanh-1 Block -- References -- Further Reading -- Exercises -- Answers -- 19.Tunable Filter -- 19.1.Tunable Filter in A Communication System -- 19.1.1.Expected Constant Bandwidth of a Tunable Filter -- 19.1.2.Variation of Bandwidth -- 19.2.Coupling between two Tank Circuits -- 19.2.1.Inappropriate Coupling -- 19.2.2.Reasonable Coupling -- 19.3.Circuit Description -- 19.4.Effect of Second Coupling -- 19.5.Performance -- Further Reading -- Exercises -- Answers -- 20.VCO (Voltage-Controlled Oscillator) -- 20.1."Three-Point" Types of Oscillator -- 20.1.1.Hartley Oscillator -- 20.1.2.Colpitts Oscillator -- 20.1.3.Clapp Oscillator -- 20.2.Other Single-Ended Oscillators -- 20.2.1.Phase-Shift Oscillator -- 20.2.2.TITO (Tuned Input and Tuned Output) Oscillator -- 20.2.3.Resonant Oscillator -- 20.2.4.Crystal Oscillator -- 20.3.VCO and PLL (Phase Lock Loop) -- 20.3.1.Implication of VCO -- 20.3.2.Transfer Function of PLL -- 20.3.3.White Noise from the Input of the PLL -- 20.3.4.Phase Noise from a VCO -- 20.4.Design Example of a Single-Ended VCO -- 20.4.1.Single-Ended VCO with Clapp Configuration -- 20.4.2.Varactor -- 20.4.3.Printed Inductor -- 20.4.4.Simulation -- 20.4.5.Load-Pulling Test and VCO Buffer -- 20.5.Differential VCO and Quad-Phases VCO -- Reference -- Further Reading -- Exercises -- Answers -- 21.PA (Power Amplifier) -- 21.1.Classification of PA -- 21.1.1.Class A Power Amplifier -- 21.1.2.Class B Power Amplifier -- 21.1.3.Class C Power Amplifier -- 21.1.4.Class D Power Amplifier -- 21.1.5.Class E Power Amplifier -- 21.1.6.Third-Harmonic-Peaking Class F Power Amplifier -- 21.1.7.Class S Power Amplifier -- 21.2.Single-Ended PA -- 21.2.1.Taming on the Bench -- 21.2.2.Simulation -- 21.3.Single-Ended PA IC Design -- 21.4.Push-Pull PA Design -- 21.4.1.Main Specification -- 21.4.2.Block Diagram -- 21.4.3.Impedance Matching -- 21.4.4.Reducing the Block Size -- 21.4.5.Double Microstrip Line Balun -- 21.4.6.Toroidal RF Transformer Balun -- 21.5.PA with Temperature Compensation -- 21.6.PA with Output Power Control -- 21.7.Linear PA -- References -- Further Reading -- Exercises -- Answers.
- Summary
- "Provides a practical scheme of wideband impedance matching for application in future circuit designs for UWB systems"--
"The author divides the book in three portions: (1) summarizes the schemes and technologies in RF circuit design, (2) describes the basic parameters of an RF system and the fundamentals of RF system design, and (3) an introduction of the individual RF circuit block design. The book begins explaining the different methodologies between RF and digital circuit design. It then moves into voltage and power transportation, impedance matching in narrow-band case and wide-band case, gain of a raw device, measurement, and grounding. Also covered are Equipotentiality and current coupling on ground surface, as well as layout and packaging, manufacturability of product design, and Radio Frequency Integrated Circuit (RFIC). Part 2 of the book includes content on the main parameters and system analysis in RF circuit design, the fundamentals of Differential Pair and Common Mode Rejection Ratio (CMRR), Balun, and System-on-a-chip (SOC). Finally, Part 3 covers Low Noise Amplifier (LNA), Mixers, Tunable Filters, Voltage-Controlled Oscillator (VCO), and Power Amplifiers (PA). All of the chapters have end-of-chapter exercises, as well as appendix"-- - Subject(s)
- ISBN
- 9781118128497
1118128494 - Bibliography Note
- Includes bibliographical references and index.
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